1. Field of the Invention
The invention relates to a shift register circuit and shift register, and more particularly, to a shift register circuit and shift register that have a stability driving circuit.
2. Description of the Prior Art
Generally, a display panel includes a plurality of pixels, gate driving circuit, and source driving circuit. The gate driving circuit includes a plurality stages of shift register and is used to provide a plurality of gate driving signals for turning on and off the pixels. The source driving circuit is used to write the data into the turned-on pixels.
FIG. 1 shows the shift register 100 according to prior art and FIG. 2 shows the timing diagram of the shift register 100 in FIG. 1. The shift register 100 includes switches T1A and T1J. The first terminal of the switch T1A receives the gate driving signal GN−1, the second terminal of the switch T1A is coupled to the node QN, and the control terminal of the switch T1A is coupled to the first terminal of the switch T1A. The first terminal of the switch T1B receives the clock signal HC1, the second terminal of the switch T1B is coupled to the output terminal Out of the shift register 100 to output the gate driving signal GN, and the control terminal of the switch T1B is coupled to the node QN. The first terminal of the switch T1C is fixed to the high gate voltage level VGH, and the control terminal of switch T1C is coupled to the first terminal of the switch T1C. The first terminal of the switch T1D is coupled to the first terminal of the switch T1C, the second terminal of the switch T1D is coupled to the node PN, and the control terminal of the switch T1D is coupled to the second terminal of the switch T1C. The first terminal of the switch T1E is coupled to the second terminal of the switch T1C, the second terminal of the switch T1E is coupled to the system voltage terminal VSS, and the control terminal of the switch T1E is coupled to the node QN. The system voltage terminal VSS is used to provide the low gate voltage level VGL. The first terminal of the switch T1F is coupled to node PN, the second terminal of the switch T1F is coupled to the system voltage terminal VSS, and the control terminal of the switch T1F is coupled to the node QN. The first terminal of the switch T1G is coupled to the node QN, the second terminal of the switch T1G is coupled to the output terminal Out, and the control terminal of the switch T1G is coupled to the node PN. The first terminal of the switch T1H is coupled to the out terminal Out, the second terminal of the switch T1H is coupled to the system voltage terminal VSS, and the control terminal of the switch T1H is coupled to the node PN. The first terminal of the switch T1I is coupled to the node QN, the second terminal of the switch T1I is coupled to the output terminal Out, and the control terminal of the switch T1I receives the gate driving signal GN+2. The first terminal of the switch T1J is coupled to the output terminal Out, the second terminal of the switch T1J is coupled to the system voltage terminal VSS, and the control terminal of the switch T1J receives the gate driving signal GN+2. The gate driving signal GN−1 is the output signal of the shift register that is one stage prior to shift register 100, and the gate driving signal GN+2 is the output signal of the shift register that is two stage next to shift register 100.
In FIG. 2, during the period of T1, the gate driving signal GN−1 is raised to the high gate voltage level VGH, the gate driving signal GN+2 is kept at the low gate voltage level VGL, and the clock signal HC1 is at the low gate voltage level VGL. The switch T1A is turned on so the voltage level of node QN is also raised to the high gate voltage level VGH. Therefore, the switch T1B is turned on and the voltage level of the gate driving signal GN is kept at the low gate voltage level VGL as the clock signal HC1. Meanwhile, the switches T1C, T1E and T1F are turned on. However, since the driving power of T1E is larger than T1C, the control terminal of the switch T1D is kept at the low gate voltage level VGL and is turned off. Since the switch T1F is turned on, the voltage level of the node PN is also kept at the low gate voltage level VGL and, thus, the switched T1G and T1H are turned off.
During the period of T2, the gate driving signals GN−1 is back to the low gate voltage level VGL, the gate driving signal GN+2 remains at the low gate voltage level VGL, and the clock signal HC1 changes to the high gate voltage level VGH. The switch T1A is turned off. The switch T1B is still turned on, which helps to pull up the voltage level of the gate driving signal GN to the high gate voltage level as the clock signal HC1. The voltage level of the node QN is raised to about two times of the high gate voltage level VGH, namely 2VGH, due to the coupling effect of the parasitic capacitor of the switch T1B. The switches T1C, T1E, and T1F are still turned on and the switches T1D, T1G, T1H, T1I, and T1J are still turned off. The voltage level of node PN remains at the low gate voltage level VGL.
During the period of T3, the gate driving signals GN−1 and GN+2 both remain at the low gate voltage level VGL, and the clock signal HC1 changes to the low gate voltage level VGL. The switch T1A is turned off. The switch T1B is turned on and helps to pull down the voltage level of the gate driving signal GN to the low gate voltage level as the clock signal HC1. Meanwhile, the node QN is floating so the voltage level of node QN will go down as the time goes by. The switches T1C, T1E, and T1F are still turned on, and the switches T1D, T1G, T1H, T1I and T1J are still turned off. The voltage level of node PN remains at the low gate voltage level VGL.
During the period of T4, the gate driving signal GN−1 remains at the low gate voltage level VGL, the gate driving signal GN+2 changes to the high gate voltage level VGH, and the clock signal HC1 changes to the high gate voltage level VGH. The switch T1A is still turned off. The switches T1I and T1J are turned on so the voltage level of the gate driving signal GN is kept at the low gate voltage level VGL and the voltage level of the node QN is pulled down to the low gate voltage level VGL as the gate driving signal GN. Meanwhile, the switch T1B, T1E, and T1F are turned off and switches T1C and T1D are turned on so the voltage level of the node PN is pulled up to the high gate voltage level VGH. Therefore, the switches T1G and T1H are turned on, which help to ensure the voltage level of the node QN and the gate driving signal GN are kept at the low gate voltage level VGL.
As the resolution of the display panel becomes higher and higher, the required time for the source driving circuit of the display panel to transmit a bit pixel is also shortened. However, since the node QN of the aforesaid shift register 100 is floating during the period of T3 in FIG. 2, the driving power of the switch T1B to pull down the voltage level of the gate driving signal GN is rather weak. Consequently, the voltage transition speed of the gate driving signal GN may not be fast enough and may cause wrong charging or wrong judgment of the display panel.